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AK5720 Datasheet(PDF) 11 Page - Asahi Kasei Microsystems |
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AK5720 Datasheet(HTML) 11 Page - Asahi Kasei Microsystems |
11 / 25 page [AK5720] MS1641-E-02 2014/12 - 11 - Parameter Symbol min typ max Unit Audio Interface Timing (Slave mode) Normal mode BICK Period BICK Pulse Width Low Pulse Width High LRCK Edge to BICK “” (Note 8) BICK “” to LRCK Edge (Note 8) LRCK to SDTO (MSB) (Except I 2S mode) BICK “” to SDTO tBCK tBCKL tBCKH tLRB tBLR tLRS tBSD 160 65 65 30 30 35 35 ns ns ns ns ns ns ns TDM256 mode BICK Period BICK Pulse Width Low Pulse Width High LRCK Edge to BICK “” (Note 8) BICK “” to LRCK Edge (Note 8) SDTO Setup time BICK “” SDTO Hold BICK “” TDMI Hold Time TDMI Setup Time tBCK tBCKL tBCKH tLRB tBLR tBSS tBSH tSDH tSDS 40 16 16 10 10 7 6 4 5 ns ns ns ns ns ns ns ns ns Audio Interface Timing (Master mode) Normal mode BICK Frequency BICK Duty BICK “” to LRCK BICK “” to SDTO fBCK dBCK tMBLR tBSD 20 40 64fs 50 20 40 Hz % ns ns TDM256 mode BICK Frequency BICK Duty (Note 9) BICK “” to LRCK SDTO Setup time BICK “” SDTO Hold BICK “” TDMI Hold Time TDMI Setup Time fBCK dBCK tMBLR tBSS tBSH tSDH tSDS 10 7 6 4 5 256fs 50 10 Hz % ns ns ns ns ns Power-Down & Reset Timing PDN Pulse Width (Note 10) PDN Reject Pulse Width (Note 10) PDN “” to SDTO valid (Note 11) tPD tRPD tPDV 150 4129 30 ns ns 1/fs Note 8. BICK rising edge must not occur at the same time as LRCK edge. Note 9. In the case of MCLK duty cycle is 50%. Note 10. The AK5720 can be reset by setting the PDN pin to “L” upon power-up. The PDN pin must held “L” for more han 150ns for a certain reset. The AK5720 is not reset by the “L” pulse less than 30ns. Note 11. This is the count of LRCK “↑” from the PDN pin = “H”. |
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