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LMX3305SLBX Datasheet(PDF) 7 Page - National Semiconductor (TI) |
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LMX3305SLBX Datasheet(HTML) 7 Page - National Semiconductor (TI) |
7 / 24 page 1.0 Functional Description The LMX3305 phase-lock-loop (PLL) system configuration consists of a high-stability crystal reference oscillator, three frequency synthesizers, three voltage controlled oscillators (VCO), and three passive loop filters. Each of the frequency synthesizers includes a phase detector, a current mode charge pump, as well as programmable reference [R] and feedback [N] frequency dividers. The VCO frequency is es- tablished by dividing the crystal reference signal down via the R-counter to obtain a comparison reference frequency. This reference signal (f R) is then presented to the input of a phase/frequency detector and compared with the feedback signal (f N), which is obtained by dividing the VCO frequency down by way of the N-counter, and fractional circuitry. The phase/frequency detector’s current source output pumps charge into the loop filter, which then converts the charge into the VCO’s control voltage. The function of phase/ frequency comparator is to adjust the voltage presented to the VCO until the feedback signal frequency and phase match that of the reference signal. When the RF PLL is in a “Phase-Locked” condition, the RF VCO frequency will be (N + F) times that of the comparison frequency, where N is the integer divide ratio, and F is the fractional component. The fractional synthesis allows the phase detector frequency to be increased while maintaining the same frequency step size for channel selection. The divider ratio N is thereby re- duced giving a lower phase noise referred to the phase de- tector input, and the comparison frequency is increased al- lowing faster switching time. 1.1 REFERENCE OSCILLATOR INPUTS The reference oscillator frequency for the RF and IF PLLs are provided from the external references through the OSC IN pin. OSC IN input can operate up to 25 MHz with input sensi- tivity of 0.5 V PP minimum and it drives RF, Rx and Tx R-counters. OSC IN input has a VCC/2 input threshold that can be driven from an external CMOS or TTL logic gate. Typically, the OSC IN is connected to the output of a crystal oscillator. 1.2 REFERENCE DIVIDERS (R-COUNTERS) The RF, Rx and Tx R-counters are clocked through the oscil- lator block. The maximum frequency is 25 MHz. All RF, Rx and Tx R-counters are CMOS design. The RF R-counter is 8-bit in length with programmable divider ratio from 2 to 255. The Rx and Tx R-counters are 10-bit in length with program- mable divider ratio from 2 to 1023. 1.3 PRESCALERS The LMX3305 has a 16/17/20/21 quadruple modulus pres- caler for the PCS application and a 8/9/12/13 quadruple modulus prescaler for the cellular application. The Rx and Tx prescalers are dual modulus with 8/9 modulus ratio. Both RF/IF prescalers’ outputs drive the subsequent CMOS flip- flop chain comprising the programmable N feedback counters. 1.4 FEEDBACK DIVIDERS (N-COUNTERS) The RF, Rx and Tx N-counters are clocked by the output of RF, Rx and Tx prescalers respectively. The RF N-counter is composed of two parts: the 15 MSB bits comprise the integer portion and the 4 LSB bits comprise the fractional portion. The RF fractional N divider is fully programmable from 80 to 32767 over the frequency range from 1200 MHz-2300 MHz for PCS application and 40 to 16383 over the frequency range from 800 MHz-1400 MHz for cellular application. The 4-bit fractional portion of the RF counter represents the frac- tion’s numerator. The fraction’s denominator base is deter- mined by the four FRAC_D register bits. The Rx and Tx N-counters are each a 13-bit integer divisor, fully programmable from 56 to 8,191 over the frequency range from 45 MHz–600 MHz. The Rx and Tx N-counters do not include fractional compensation. 1.5 FRACTIONAL COMPENSATION The fractional compensation circuitry of the LMX3305 RF di- vider allows the user to adjust the VCO tuning resolution in 1/2 through 1/16th increments of the phase detector com- parison frequency. A 4-bit denominator register (FRAC_D) selects the fractional modulo base. The integer averaging is accomplished by using a 4-bit accumulator. A variable phase delay stage compensates for the accumulated integer phase error, minimizes the charge pump duty cycle and reduces the spurious levels. This technique eliminates the need for compensation current injection into the loop filter. An over- flow signal generated by the accumulator is equivalent to one full RF VCO cycle, and results in a pulse swallow. 1.6 PHASE/FREQUENCY DETECTORS The RF and IF phase/frequency detectors are driven from their respective N- and R-counter outputs. The maximum fre- quency at the phase detector inputs is 10 MHz unless limited by the minimum continuous divide ratio of the multi-modulus prescaler. The phase detector output controls the charge pump. The polarity of the pump-up or pump-down control is programmed using RF_PD_POL, Rx_PD_POL,or Tx_PD_POL depending on whether RF or IF VCO charac- teristics are positive or negative. The phase detector also re- ceives a feedback signal from the charge pump in order to eliminate dead zones. 1.7 CHARGE PUMPS The phase detector’s current source output pumps charge into an external loop filter, which then converts it into the VCO’s control voltage. The charge pump steers the charge pump output CP o to V CC (pump-up) or Ground (pump- down). When locked, CP o is primarily in a TRI-STATE mode with small corrections. The IF charge pump output current magnitudes are nominally 100 µA. The RF charge pump out- put currents can be programmed by the RF_Icpo bits at 100 µA, 400 µA, 700 µA, or 900 µA. 1.8 VOLTAGE DOUBLER (V P) The V P pin is normally driven from an external power supply over a range of V CC to 5.5V to provide current for the RF charge pump circuit. An internal voltage doubler circuit con- nected between the V CC and VP supply pins alternately al- lows V CC =3V(±10%) users to run the RF charge pump cir- cuit at close to twice the V CC power supply voltage. The voltage doubler mode is enabled by setting the V2X bit to a HIGH level. The voltage doubler’s charge pump driver origi- nates from the oscillator input. The device will not totally powerdown until the V2X bit is programmed LOW. The aver- age delivery current of the doubler is less than the instanta- neous current demand of the RF charge pump when active and is thus not capable of sustaining a continuous out of lock condition. A large external capacitor connected to V P (=0.1 µF) is needed to control power supply droop when changing frequencies. www.national.com 7 |
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