MYSON

TECHNOLOGY

MTV016

MTV016 Revision 2.0 01/01/1999

6/11

The internal RAM contains display and row control registers. The display registers have 240 locations

that are allocated between row 0/column 0 and row 9/column 23, as shown in Figure 5. Each display

register has a blink bit, and its corresponding character address on the ADDRESS byte and 2 color

selection bits on the ATTRIBUTE bytes. The row control register is allocated between columns 28 and

31 for rows 0 to 9; it is used to set character size and color attribute for each respective row. If double

width character is chosen, only even column characters may be displayed on-screen and the odd

column characters will be hidden.

COLUMN #

ROW #

0

23

24

27

28

31

0

1

8

9

DISPLAY

REGISTERS

RESERVED

ROW

CTRL REG

COLUMN #

0

2

3

5

6

8

9

11

12

17

ROW 10

WINDOW1

WINDOW2

WINDOW3

WINDOW4

FRAME

CTRL REG

Figure 5. Memory Map

Register Descriptions

(i) Display Register

ADDRESS BYTE

b7

b6

b5

b4

b3

b2

b1

b0

BLINK

←

CRADDR

→

BLINK - Enables a blinking effect when this bit is set to " 1 ". The blinking alternates every 32 frames.

CRADDR - Defines the display character address and graphic symbols in ROM.

ATTRIBUTE BYTE

b7

b6

b5

b4

b3

b2

b1

b0

CCS1

CCS0

-

-

-

-

-

-

CCS1, CCS0 - These bits are used to select character color. Color 1 will be selected if these bits are set

to 0/0, color 2 will be selected if these bits are set to 0/1, color 3 will be selected if these

bits are set to 1/0 and color 4 will be selected if these bits are set to 1/1. Color 1, color 2,

color 3 and color 4 are defined in the respective row control registers.