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SMJ416400 Datasheet(PDF) 6 Page - Texas Instruments

No. de pieza SMJ416400
Descripción Electrónicos  4194304 BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY
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Fabricante Electrónico  TI [Texas Instruments]
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SMJ416400 Datasheet(HTML) 6 Page - Texas Instruments

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SMJ416400
4194304 BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS042E – MARCH 1992 – REVISED MARCH 1996
6
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (see Note 6)
PARAMETER
’416400 - 70
’416400 - 80
’416400 - 10
UNIT
PARAMETER
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
tAA
Access time from column-address
35
40
45
ns
tCAC
Access time from CAS low
18
20
25
ns
tCPA
Access time from column precharge
40
45
50
ns
tRAC
Access time from RAS low
70
80
100
ns
tOEA
Access time from OE low
18
20
25
ns
tOFF
Output disable time after CAS high (see Note 7)
0
18
0
20
0
25
ns
tOEZ
Output disable time after OE high (see Note 7)
0
18
0
20
0
25
ns
NOTES:
6. Valid data is presented at the outputs after all access times are satisfied but can go from the high-impedance state to an invalid-data
state prior to the specified access times as the outputs are driven when CAS goes low.
7. tOFF and tOEZ are specified when the outputs are no longer driven. The outputs are disabled by bringing either OE or CAS high.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
’416400 - 70
’416400 - 80
’416400 - 10
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
tRC
Cycle time, random read or write (see Note 8)
130
150
180
ns
tRWC
Cycle time, read-write (see Note 8)
181
205
245
ns
tPC
Cycle time, page mode read or write (see Notes 8 and 9)
45
50
55
ns
tPRWC
Cycle time, page mode read-write (see Note 8)
96
105
120
ns
tRASP
Pulse duration, RAS low, page mode (see Note 10)
70
100 000
80
100 000
100
100 000
ns
tRAS
Pulse duration, RAS low, nonpage mode (see Note 10)
70
10 000
80
10 000
100
10 000
ns
tCAS
Pulse duration, CAS low (see Note 11)
18
10 000
20
10 000
25
10 000
ns
tCP
Pulse duration, CAS high
10
10
10
ns
tRP
Pulse duration, RAS high (precharge)
50
60
70
ns
tWP
Pulse duration, W low
10
10
10
ns
tASC
Setup time, column address before CAS going low
0
0
0
ns
tASR
Setup time, row address before RAS going low
0
0
0
ns
tDS
Setup time, data (see Note 12)
0
0
0
ns
tRCS
Setup time, W high before CAS going low
0
0
0
ns
tCWL
Setup time, W low before CAS going high
18
20
25
ns
tRWL
Setup time, W low before RAS going high
18
20
25
ns
tWCS
Setup time, W low before CAS going low
(early-write operation only)
0
0
0
ns
tWRP
Setup time, W high before RAS going low (CBR refresh only)
10
10
10
ns
tCAH
Hold time, column address after CAS low
15
15
15
ns
tDH
Hold time, data (see Note 12)
15
15
15
ns
tRAH
Hold time, row address after RAS low
10
10
10
ns
tRCH
Hold time, W high after CAS high (see Note 13)
0
0
0
ns
tRRH
Hold time, W high after RAS high (see Note 13)
0
0
5
ns
NOTES:
8. All cycle times assume tT = 5 ns, referenced to VIH(min) and VIL(max).
9. To assure tPC min, tASC should be ≥ tCP .
10. In a read-write cycle, tRWD and tRWL must be observed.
11. In a read-write cycle, tCWD and tCWL must be observed.
12. Referenced to the later of CAS or W in write operations
13. Either tRRH or tRCH must be satisfied for a read cycle.


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