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TPS54356PWP Datasheet(PDF) 11 Page - Texas Instruments

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No. de pieza TPS54356PWP
Descripción Electrónicos  4.5V TO 20 V INPUT 3-A OUTPUT SYNCHRONOUS PWM SWITCHER WITH INTEGRATED FET
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Fabricante Electrónico  TI [Texas Instruments]
Página de inicio  http://www.ti.com
Logo TI - Texas Instruments

TPS54356PWP Datasheet(HTML) 11 Page - Texas Instruments

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TPS54352,TPS54353
TPS54354,TPS54355
TPS54356,TPS54357
SLVS519 − MAY 2004
www.ti.com
11
Internal Oscillator
VO(PH)
VO(SYNC)
Figure 4. SYNC Output Waveform
Power Good (PWRGD)
The VSENSE pin is compared to an internal reference
signal, if the VSENSE is greater than 97% and no other
faults are present, the PWRGD pin presents a high
impedance. A low on the PWRGD pin indicates a fault. The
PWRGD pin has been designed to provide a weak
pull-down and indicates a fault even when the device is
unpowered. If the TPS5435x has power and has any fault
flag set, the TPS5435x indicates the power is not good by
driving the PWRGD pin low. The following events, singly
or in combination, indicate power is not good:
D VSENSE pin out of bounds
D Overcurrent
D Thermal shutdown
D UVLO undervoltage
D Input voltage not present (weak pull-down)
D Slow-starting
D VBIAS voltage is low
Once the PWRGD pin presents a high impedance (i.e.,
power is good), a VSENSE pin out of bounds condition
forces PWRGD pin low (i.e., power is bad) after a time
delay. This time delay is a function of the switching
frequency and is calculated using equation 6:
T
delay +
1000
ƒs(kHz)
ms
Bias Voltage (VBIAS)
The VBIAS regulator provides a stable supply for the
internal analog circuits and the low side gate driver. Up to
1 mA of current can be drawn for use in an external
application circuit. The VBIAS pin must have a bypass
capacitor value of 1.0
µF. X7R or X5R grade dielectric
ceramic capacitors are recommended because of their
stable characteristics over temperature.
Bootstrap Voltage (BOOT)
The BOOT capacitor obtains its charge cycle by cycle from
the VBIAS capacitor. A capacitor from the BOOT pin to the
PH pins is required for operation. The bootstrap
connection for the high side driver must have a bypass
capacitor of 0.1
µF.
Error Amplifier
The VSENSE pin is the error amplifier inverting input. The
error amplifier is a true voltage amplifier with 1.5 mA of
drive capability with a minimum of 60 dB of open loop
voltage gain and a unity gain bandwidth of 2 MHz.
Voltage Reference
The voltage reference system produces a precision
reference signal by scaling the output of a temperature
stable bandgap circuit. During production testing, the
bandgap and scaling circuits are trimmed to produce
0.891 V at the output of the error amplifier, with the
amplifier connected as a voltage follower. The trim
procedure improves the regulation, since it cancels offset
errors in the scaling and error amplifier circuits.
PWM Control and Feed Forward
Signals from the error amplifier output, oscillator, and
current limit circuit are processed by the PWM control
logic. Referring to the internal block diagram, the control
logic includes the PWM comparator, PWM latch, and the
adaptive dead-time control logic. During steady-state
operation below the current limit threshold, the PWM
comparator output and oscillator pulse train alternately
reset and set the PWM latch.
(6)


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