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TPS3808G30DBVRG4 Datasheet(PDF) 8 Page - Texas Instruments |
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TPS3808G30DBVRG4 Datasheet(HTML) 8 Page - Texas Instruments |
8 / 15 page www.ti.com DEVICE OPERATION SENSE INPUT RESET OUTPUT V IN TPS3808G01 V D D SENSE GND RESET R 1 R 2 1nF V IT′ = (1 + )0.405 R 1 R 2 V OUT MANUAL RESET (MR) INPUT 2.5V T PS 380 8G 25 O M AP 1510 V DD SENSE V DDSHV 1, 3, 6, 7, 9 GND GND C T MR RESET 1M Ω RESPWRON TPS3808 SBVS050E – MAY 2004 – REVISED OCTOBER 2005 supply line can be used to allow the reset signal for The TPS3808 microprocessor supervisory product the microprocessor to have a voltage higher than VDD family is designed to assert a RESET signal when (up to 6.5V). The pull-up resistor should be no either the SENSE pin voltage drops below VIT or the smaller than 10k Ω as a result of the finite impedance manual reset (MR) is driven low. The RESET output of the RESET line. remains asserted for a user-adjustable time after both the manual reset (MR) and SENSE voltages return above their thresholds. A broad range of voltage threshold and reset delay time adjustments are The SENSE input provides a terminal at which any available, allowing these devices to be used in a wide system voltage can be monitored. If the voltage on array of applications. Reset threshold voltages can be this pin drops below VIT, then RESET is asserted. factory-set from 0.82V to 3.3V or from 4.4V to 5.0V, The comparator has a built-in hysteresis to ensure while the TPS3808G01 can be set to any voltage smooth RESET assertions and de-assertions. It is above 0.405V using an external resistor divider. Two good analog design practice to put a 1nF to 10nF preset delay times are also user-selectable: bypass capacitor on the SENSE input to reduce connecting the CT pin to VDD results in a 300ms reset sensitivity to transients and layout parasitics. delay, while leaving the CT pin open yields a 20ms The TPS3808G01 can be used to monitor any reset delay. In addition, connecting a capacitor voltage rail down to 0.405V using the circuit shown in between CT and GND allows the designer to select Figure 11. any reset delay period from 1.25ms to 10s. A typical application of the TPS3808G25 used with the OMAP1510 processor is shown in Figure 10. The open drain RESET output is typically connected to the RESET input of a microprocessor. A pull-up resistor must be used to hold this line high when RESET is not asserted. The RESET output is undefined for voltage below 0.8V, but this is normally not a problem since most microprocessors do not function below this voltage. RESET remains high Figure 11. Using the TPS3808G01 to Monitor a (unasserted) as long as SENSE is above its threshold User-Defined Threshold Voltage (VIT) and the manual reset (MR) is logic high. If either SENSE falls below VIT or MR is driven low, RESET is asserted, driving the RESET pin to a low impedance. The manual reset (MR) input allows a processor or other logic circuits to initiate a reset. A logic low (0.3VDD) on MR causes RESET to assert. After MR returns to a logic high and SENSE is above its reset threshold, RESET is de-asserted after the user defined reset delay expires. Note that MR is internally tied to VDD using a 90kΩ resistor so this pin can be left unconnected if MR will not be used. See Figure 12 for how MR can be used to monitor multiple system voltages. Note that if the logic signal Figure 10. Typical Application of the TPS3808 driving MR does not go fully to VDD, there will be with an OMAP Processor some additional current draw into VDD as a result of the internal pull-up resistor on MR. To minimize Once MR is again logic high and SENSE is above VIT current draw, a logic-level FET can be used as + VHYS (the threshold hysteresis), a delay circuit is illustrated in Figure 13. enabled which holds RESET low for a specified reset delay period. Once the reset delay has expired, the RESET pin goes to a high impedance state. The pull-up resistor from the open drain RESET to the 8 |
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