RTN

PG

TPS2373

VC_IN

VC_OUT

Xfrmer Aux

Bias Supply

Vc

SS

PWM

UCC2897A

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11

TPS2373

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SLUSCD1 – APRIL 2017

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Feature Description (continued)

•

Internal pass MOSFET is turned off

•

Classification current is disabled

•

PG, TPL and BT outputs are forced to high impedance

•

TPH output is turned on (low state)

•

PWM startup is enabled without any inrush delay

•

Maintain Power Signature (MPS) pulsed mode is enabled

provides input voltage supervision to ensure that switch-over to the auxiliary voltage source does not occur at

excessively low voltages. If not used, connect APD to RTN.

7.3.2 PG Power Good (Converter Enable) Pin Interface

PG is an active high output that is pulled to RTN when the device is in inrush phase. It remains in a high

impedance state at all other times. This pin is an open-drain output, and it may require a pullup resistor or other

interface to the downstream load. PG may be left open if it is not used.

The PG pin can be used to inhibit downstream converter startup by keeping the soft-start pin low. Figure 1 shows

an example where PG connects to the SS pin of a DC-DC controller. Because PG is an open drain output, it will

not affect the soft-start capacitor charge time when it deasserts. Another common use of the PG pin is to enable

a converter with an active-high enable input. In this case, PG may require a pullup resistor to either VDD, or to a

bias supply, depending on the requirements of the controller enable pin.

Figure 1. PG Interface

7.3.3 CLSA and CLSB Classification

class event) and CLSB (third and any subsequent class event) pins and VSS provide a distinct classification

signature to the PSE, and are used to define the power class requested by the PD. The controller places a

voltage of approximately 2.5 V across CLSA (first or second class event) or CLSB (all additional class events)

external resistor whenever the voltage differential between VDD and VSS lies from about 10.9 V to 22 V. The

current drawn by each resistor, combined with the internal current drain of the controller and any leakage through

the internal pass MOSFET, creates the classification signature current. Table 1 lists the external resistor values

required for each of the PD power ranges defined by IEEE802.3bt. The number of classification cycles then

determines how much power is allocated by the PSE. The maximum average power drawn by the PD, plus the

power supplied to the downstream load, should not exceed the maximum power indicated in Table 1, as well as

the maximum power allocated by the PSE based on the number of classification cycles. Holding APD high

disables the classification signatures.