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ADC08D1520WGFQV Datasheet(PDF) 1 Page - Texas Instruments

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No. de pieza ADC08D1520WGFQV
Descripción Electrónicos  Low Power, 8-Bit, Dual 1.5 GSPS or Single 3.0 GSPS A/D Converter
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Fabricante Electrónico  TI1 [Texas Instruments]
Página de inicio  http://www.ti.com
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ADC08D1520WGFQV Datasheet(HTML) 1 Page - Texas Instruments

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ADC08D1520QML-SP
www.ti.com
SNAS420O – JANUARY 2008 – REVISED MARCH 2013
ADC08D1520QML Low Power, 8-Bit, Dual 1.5 GSPS or Single 3.0 GSPS A/D Converter
1
FEATURES
DESCRIPTION
The ADC08D1520 is an 8–Bit, dual channel, low
2
Total Ionizing Dose 300 krad(Si)
power, high performance CMOS analog-to-digital
Single Event Latch-up 120 MeV-cm2/mg
converter that builds upon the ADC08D1000 platform.
Single +1.9V ±0.1V Operation
The ADC08D1520 digitizes signals to 8 bits of
resolution at sample rates up to 1.7 GSPS. It has
Interleave Mode for 2x Sample Rate
expanded features compared to the ADC08D1000,
Multiple ADC Synchronization Capability
which include a test pattern output for system debug,
Adjustment of Input Full-Scale Range, Offset
clock
phase
adjust,
and
selectable
output
and Clock Phase Adjustment
demultiplexer modes. Consuming a typical 2.0W in
Demultiplex Mode at 1.5 GSPS from a single 1.9 Volt
Choice of SDR or DDR output clocking
supply, this device is ensured to have no missing
1:1 or 1:2 Selectable Output Demux
codes over the full operating temperature range. The
Second DCLK output
unique folding and interpolating architecture, the fully
differential comparator design, the innovative design
Duty Cycle Corrected Sample Clock
of the internal sample-and-hold amplifier and the self-
Test pattern
calibration scheme enable a very flat response of all
Serial Interface for Extended Control
dynamic parameters beyond Nyquist, producing a
high 7.2 Effective Number of Bits (ENOB) with a 748
KEY SPECIFICATIONS
MHz input signal and a 1.5 GHz sample rate while
providing a 10-18 Code Error Rate (C.E.R.) Output
Resolution 8 Bits
formatting is offset binary and the Low Voltage
Max Conversion Rate 1.5 GSPS (min)
Differential Signaling (LVDS) digital outputs are
compatible
with
IEEE
1596.3-1996,
with
the
Code Error Rate 10-18 (typ)
exception of an adjustable common mode voltage
ENOB at 748 MHz Input 7.2 Bits (typ)
between 0.8V and 1.2V.
DNL ±0.15 LSB (typ)
Each converter has a selectable output demultiplexer
Power Consumption
which
feeds
two
LVDS
buses.
If
the
1:2
Operating in 1:2 Demux Output 2.0 W (typ)
Demultiplexed Mode is selected, the output data rate
is reduced to half the input sample rate on each bus.
Power Down Mode 2.9 mW (typ)
When Non-Demultiplexed Mode is selected, the
output data rate on channels DI and DQ are at the
APPLICATIONS
same rate as the input sample clock. The two
Direct RF Down Conversion
converters can be interleaved and used as a single 3
Digital Oscilloscopes
GSPS ADC.
Communications Systems
The converter typically consumes less than 2.9 mW
in the Power Down Mode and is available in a 128-
Test Instrumentation
pin, thermally enhanced, multi-layer ceramic quad
package and operates over the Military (-55°C
≤ TA
+125°C) temperature range.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2008–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.


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