AD9649_17 datasheet(8/33 Pages) AD

No. de pieza	AD9649

Descripción Electrónicos	14-Bit, 20/40/65/80 MSPS, 1.8 V Analog-to-Digital Converter

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Data Sheet

AD9649

Rev. B | Page 7 of 32

SWITCHING SPECIFICATIONS

AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty

cycle clock, unless otherwise noted.

Table 4.

Parameter

Temp

AD9649-20/AD9649-40

AD9649-65

AD9649-80

Unit

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

CLOCK INPUT PARAMETERS

Input Clock Rate

Full

80/160

260

320

MHz

Conversion Rate1

Full

3

20/40

3

65

3

80

MSPS

CLK Period, Divide-by-1 Mode (tCLK)

Full

50/25

15.38

12.5

ns

CLK Pulse Width High (tCH)

25.0/12.5

7.69

6.25

ns

Aperture Delay (tA)

Full

1.0

ns

Aperture Uncertainty (Jitter, tJ)

Full

0.1

ps rms

DATA OUTPUT PARAMETERS

Data Propagation Delay (tPD)

Full

3

ns

DCO Propagation Delay (tDCO)

Full

3

ns

DCO to Data Skew (tSKEW)

Full

0.1

ns

Pipeline Delay (Latency)

Full

8

Cycles

Wake-Up Time2

Full

350

µs

Standby

Full

600/400

300

260

ns

OUT-OF-RANGE RECOVERY TIME

Full

2

Cycles

1

Conversion rate is the clock rate after the CLK divider.

2

Wake-up time is dependent on the value of the decoupling capacitors.

tPD

tSKEW

tCH

tDCO

tCLK

N – 8

N – 1

N + 1

N + 2

N + 3

N + 5

N + 4

N

N – 7

N – 6

N – 5

N – 4

VIN

CLK+

CLK–

DATA

DCO

tA

Figure 2. CMOS Output Data Timing

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Descripción similar - AD9649_17

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Analog Devices	AD9649	1Mb / 32P	14-Bit, 20/40/65/80 MSPS, 1.8 V Analog-to-Digital Converter REV. 0
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AD9649 Datasheet(PDF) 8 Page - Analog Devices

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