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TPS7A65-Q1 Datasheet(PDF) 4 Page - Texas Instruments |
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TPS7A65-Q1 Datasheet(HTML) 4 Page - Texas Instruments |
4 / 26 page TPS7A6533-Q1, TPS7A6550-Q1 SLVSA98D – MAY 2010 – REVISED DECEMBER 2015 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT VIN Unregulated input(2)(3) 45 V VOUT Regulated output 7 V θJP Thermal impedance junction to exposed pad 1.2 °C/W TA Operating ambient temperature 125 °C Tstg Storage temperature –65 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) Absolute negative voltage on these pins not to go below –0.3 V. (3) Absolute maximum voltage for duration less than 480 ms. 6.2 ESD Ratings VALUE UNIT V(ESD) Electrostatic discharge Human body model (HBM), per AEC Q100-002(1) ±2000 V (1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification. 6.3 Recommended Operating Conditions MIN MAX UNIT VIN Unregulated input voltage 4 40 V TJ Operating junction temperature –40 150 °C 6.4 Thermal Information TPS7A65xx-Q1 THERMAL METRIC(1) KVU (TO-252) UNIT 3 PINS High-K profile(2) 29.3 °C/W RθJA Junction-to-ambient thermal resistance Low-K profile(3) 38.6 °C/W RθJC(top) Junction-to-case (top) thermal resistance N/A °C/W RθJB Junction-to-board thermal resistance 8.2 °C/W ψJT Junction-to-top characterization parameter 3.4 °C/W ψJB Junction-to-board characterization parameter 8.1 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 1.1 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. (2) The thermal data is based on JEDEC standard high-K profile – JESD 51-5. The copper pad is soldered to the thermal land pattern. Also correct attachment procedure must be incorporated. (3) The thermal data is based on JEDEC standard low-K profile – JESD 51-3. The copper pad is soldered to the thermal land pattern. Also correct attachment procedure must be incorporated. 4 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: TPS7A6533-Q1 TPS7A6550-Q1 |
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