TPS715

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SLVS338R – MAY 2001 – REVISED APRIL 2015

Feature Description (continued)

7.3.4 Internal Current Limit

The internal current limit circuit is used to protect the LDO against high-load current faults or shorting events. The

LDO is not designed to operate in a steady-state current limit. During a current limit event, the LDO sources

constant current. Therefore, the output voltage falls when load impedance decreases.

NOTE

if a current limit occurs and the resulting output voltage is low, excessive power is

dissipated across the LDO, resulting in possible damage to the device.

7.3.5 Reverse Current

The TPS715 PMOS-pass transistor has a built-in back diode that conducts current when the input voltage drops

below the output voltage (for example, during power down). Current is conducted from the output to the input and

is not internally limited. If extended reverse voltage operation is anticipated, external limiting may be required.

7.4 Device Functional Modes

Table 1 provides a quick comparison between the normal, dropout, and disabled modes of operation.

Table 1. Device Functional Mode Comparison

PARAMETER

OPERATING MODE

Normal

Dropout

Disabled

—

—

7.4.1 Normal Operation

The device regulates to the nominal output voltage under the following conditions:

•

•

•

The device junction temperature is less than 125°C.

7.4.2 Dropout Operation

If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other

conditions are met for normal operation, the device operates in dropout mode. In this mode, the output voltage

tracks the input voltage. During this mode, the transient performance of the device becomes significantly

degraded because the pass device is in the linear region and no longer controls the current through the LDO.

Line or load transients in dropout can result in large output-voltage deviations.

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