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TPS71334 Datasheet(PDF) 9 Page - Texas Instruments |
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TPS71334 Datasheet(HTML) 9 Page - Texas Instruments |
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9 / 20 page  www.ti.com APPLICATION INFORMATION OUTPUT NOISE TPS71334 GND NR FB2 IN OUT1 EN1 OUT2 EN2 RESET V IN V OUT1 V OUT2 0.1 µF 2.2 µF 2.2 µF C1 100 k Ω 0.01 µF R1 R2 64.9 k Ω INPUT AND OUTPUT CAPACITOR STARTUP CHARACTERISTICS TPS71319 TPS71334 SBVS055A – DECEMBER 2004 – REVISED JANUARY 2005 1.8 V or less is chosen, the minimum recommended The TPS713xx family of dual low-dropout (LDO) output capacitor is 4.7 µF. Any ceramic capacitor that regulators has been optimized for use in meets the minimum output capacitor requirements is noise-sensitive battery-operated equipment. The de- suitable. Capacitors with higher ESR may be used, vice features extremely low dropout, high PSRR, provided the worst-case ESR is less than 1 Ω. ultralow output noise, and low quiescent current (190 µA typically per channel). When both outputs are disabled, the supply currents are reduced to less than 2µA. A typical application circuit with sequencing The internal voltage reference is a key source of is shown in Figure 24. noise in an LDO regulator. The TPS713xx has an NR pin that is connected to the voltage reference through a 250 k Ω internal resistor. The 250 kΩ internal resistor, in conjunction with an external ceramic bypass capacitor connected to the NR pin, creates a low-pass filter to reduce the voltage reference noise and, therefore, the noise at the regulator output. To achieve a fast startup, the 250 k Ω internal resistor is shorted for 400 µs after the device is enabled. Because the primary noise source is the internal voltage reference, the output noise will be greater for higher output voltage versions. For the case where no noise reduction capacitor is used, the typical noise (µVrms) over 10 Hz to 100 kHz is 30 times the output voltage. If a 0.01 µF capacitor is used from the NR pin to ground, the noise (µVrms) drops to 11.8 times Figure 24. Typical Application Circuit the output voltage. For example, the TPS71334 with (with output sequencing) the adjustable output set to 2.8 V exhibits only 33 µVrms of output voltage noise using a 0.01 µF ceramic bypass capacitor and a 2.2 µF ceramic output capacitor. REQUIREMENTS A 0.1 µF or larger ceramic input bypass capacitor, connected between IN and GND and located close to To minimize startup overshoot, the TPS713xx will the TPS713xx, is required for stability. It improves initially target an output voltage that is approximately transient response, noise rejection, and ripple rejec- 80% of the final value. To avoid a delayed startup tion. A higher-value input capacitor may be necessary time, noise reduction capacitors of 0.01 µF or less if large, fast-rise-time load transients are anticipated are recommended. Larger noise reduction capacitors and the device is located several inches from the will cause the output to hold at 80% until the voltage power source. on the noise reduction capacitor exceeds 80% of the The TPS713xx requires an output capacitor connec- bandgap voltage. The typical startup time with a ted between the outputs and GND to stabilize the 0.001 µF noise reduction capacitor is 60 µs. Once internal control loops. The minimum recommended one of the output voltages is present, the startup time output capacitor is 2.2 µF. If an output voltage of of the other output will not be affected by the noise reduction capacitor. 9 |
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