10

15

0.5

0

1.0

1.5

2.0

2.5

3.0

20

25

30

35

40

45

50

45

UNDERVOLTAGE LOCKOUT

vs

HYSTERESIS

UDG-02132

Clock

PWM RAMP

PowerGood

VIN

UVLO Threshold

1 2 3 4 5 6 7

1 2 3 4 5 6 7

1 2

TPS40060

TPS40061

www.ti.com

SLUS543F – DECEMBER 2002 – REVISED JUNE 2013

where:

•

•

(3)

The variable UVLO function utilizes a 3-bit full adder to prevent spurious shut-downs or turn-ons due to spikes or

fast line transients. When the adder reaches a total of seven counts in which the ramp duration is shorter the

clock cycle a powergood signal is asserted, a soft-start initiated, and the upper and lower MOSFETs are turned

off.

Once the soft-start is initiated, the UVLO circuit must see a total count of seven cycles in which the ramp

duration is longer than the clock cycle before an undervoltage condition is declared (See Figure 4).

Figure 4. Undervoltage Lockout Operation

Figure 5.

Copyright © 2002–2013, Texas Instruments Incorporated

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