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ADV7185 Datasheet(PDF) 8 Page - Analog Devices |
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ADV7185 Datasheet(HTML) 8 Page - Analog Devices |
8 / 40 page REV. 0 –8– ADV7185 PIN FUNCTION DESCRIPTIONS (continued) Pin Mnemonic Input/Output Function 39, 40, 47, 53, AVSS G Ground for Analog Supply 56, 63 41, 43, 45, 57, AVSS1–AVSS6 G Analog Input Channels. Ground if single-ended mode is selected. These pins 59, 61 should be connected directly to REFOUT when differential mode is selected. 42, 44, 46, 58, AIN1–AIN6 I Video Analog Input Channels 60, 62 48, 49 CAPY1–CAPY2 I ADC Capacitor Network 50 AVDD P Analog Supply Voltage (5 V) 51 REFOUT O Internal Voltage Reference Output 52 CML O Common-Mode Level for ADC 54, 55 CAPC1–CAPC2 I ADC Capacitor Network 64 RESET I System Reset Input. Active Low 65 ISO I Input Switch Over. A low to high transition on this input indicates to the decoder core that the input video source has been changed externally and configures the decoder to reacquire the new timing information of the new source. This is useful in applications where external video muxes are used. This input gives the advantage of faster locking to the external muxed video sources. A low to high transition triggers this input. 66 ALSB I TTL Address Input. Selects the MPU address: MPU address = 88h ALSB = 0, disables I 2C filter MPU address = 8Ah ALSB = 1, enables I 2C filter 67 SDATA I/O MPU Port Serial Data Input/Output 68 SCLOCK I MPU Port Serial Interface Clock Input 69 VREF/ VRESET O VREF or Vertical Reference Output Signal. Indicates start of next field. VRESET or Vertical Reset Output is a signal that indicates the beginning of a new field. In SCAPI/CAPI mode this signal is one clock wide and active low relative to CLKIN. It immediately follows the HRESET pixel, and indicates that the next active pixel is the first active pixel of the next field. 70 HREF/ HRESET O HREF or Horizontal Reference Output Signal. A dual-function pin (enabled when Line-Locked Interface is selected, OM_SEL[1:0] = 0,0), this signal is used to indicate data on the YUV output. The positive slope indicates the beginning of a new active line, HREF is always 720 Y samples long. HRESET or Horizontal Reset Output (enabled when SCAPI or CAPI is selected, OM_SEL[1:0] = 0, 1 or 1, 0) is a signal that indicates the beginning of a new line of video. In SCAPI/CAPI this signal is one clock cycle wide and is output relative to CLKIN. It immediately follows the last active pixel of a line. The polarity is controlled via PHVR. 77 RD I Asynchronous FIFO Read Enable Signal. A logical high on this pin enables a read from the output of the FIFO. 78 DV O DV or Data Valid Output Signal. In SCAPI/CAPI mode, DV performs two functions, depending on whether SCAPI or CAPI is selected. It toggles high when the FIFO has reached the AFF margin set by the user, and remains high until the FIFO is empty. The alternative mode is where it can be used to control FIFO reads for bursting information out of the FIFO. In API mode DV indicates valid data in the FIFO, which includes both pixel information and control codes. The polarity of this pin is con- trolled via PDV. 79 OE IOutput Enable Controls Pixel Port Outputs. A logic high will three-state P19–P0. 80 FIELD O ODD/EVEN Field Output Signal. An active state indicates that an even field is being digitized. The polarity of this signal is controlled by the PF bit. |
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