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ACE25AC400GL Datasheet(PDF) 4 Page - ACE Technology Co., LTD. |
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ACE25AC400GL Datasheet(HTML) 4 Page - ACE Technology Co., LTD. |
4 / 23 page ACE25AC400GL SPI NOR FLASH VER 1.1 4 Device Operation The ACE25AC400GL features a serial peripheral interface on 4 signals bus: Serial Clock (SCLK), Chip Select (CS#), Serial Data Input (SI) and Serial Data Output (SO). Both SPI bus mode 0 and 3 are supported. Input data is latched on the rising edge of SCLK and data shifts out on the falling edge of SCLK. Data Protection The ACE25AC400GL provides the following data protection methods: Write Enable (WREN) command: The WREN command is set the Write Enable Latch bit (WEL). The WEL bit will return to reset by the following situation: Power-Up Write Disable (WRDI) Write Status Register (WRSR) Page Program (PP) Sector Erase (SE) / Block Erase (BE) / Chip Erase (CE) Software Protection Mode: SRWD=0, the Block Protect (BP2, BP1, BP0) bits define the section of the memory array that can be read but not change SRWD=1, the Write Status Register (WRSR) instruction is no longer accepted for execution and the SRWD bit and Block Protect bits (BP2, BP1, BP0) are read only. Table 1.ACE25AC400GL Protected Area Sizes Status bit Protect level Protect Block BP2 BP1 BP0 0 0 0 0(none) None 0 0 1 1 (1 block) Block 7 0 1 0 2 (2 blocks) Block 6-7 0 1 1 3 (4 blocks) Block 4-7 1 0 0 4 (8 blocks) All 1 0 1 5 (All) All 1 1 0 6 (All) All 1 1 1 7 (All) All |
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