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TS83102G0B Datasheet(PDF) 5 Page - ATMEL Corporation |
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TS83102G0B Datasheet(HTML) 5 Page - ATMEL Corporation |
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5 / 56 page  5 TS83102G0B 2101D–BDC–06/04 Analog input power level (50 Ω single-ended) 4 PIN - 2 dBm Analog input capacitance (die) 4 C IN 0.3 pF Input leakage current 4 IIN 10 µA Input resistance - single-ended - differential 4 4 RIN R IN 49 98 50 100 51 102 Ω Ω Clock Inputs Logic common mode compatibility for clock inputs Differential ECL to LVDS Clock inputs common voltage range (V CLK or VCLKB) (DC coupled clock input) AC coupled for LVDS compatibility (common mode 1.2V) 4V CM -1.2 0 0.3 V Clock input power level (low-phase noise sinewave input) 50 Ω single-ended or 100 Ω differential 4PCLK -4 0 4 dBm Clock input swing (single ended; with CLKB = 50 Ω to GND) 4V CLK ±200 ±320 ±500 mV Clock input swing (differential voltage) - on each clock input 4 V CLK VCLKB ±141 ±226 ±354 mV Clock input capacitance (die) 4 C CLK 0.3 pF Clock input resistance - single-ended - differential ended R CLK RCLK 45 90 50 100 55 110 Ω Ω Digital Inputs (SDAEN, PGEB, DECB/Diode, B/GB, DRRB) - logic low - logic high 4 V IL V IH -5 -2 -3 0 V V Digital Inputs (DRRB Only) Logic Compatibility Negative ECL - logic low - logic high 4 VIL V IH -1.810 -1.165 -1.625 -0.880 V V Electrical Operating Characteristics (Continued) V CC = 5V ; VPLUSD = 0V (unless otherwise specified). ADC performances are independent of VPLUSD common mode voltage and performances are guaranteed within the limits of the specified V PLUSD range (from -0.9V to 1.7V); V EE = DVEE = -5V; VIN - VINB = 500 mVpp (full-scale single-ended or differential input); clock inputs differential driven; analog-input single-ended driven. Parameter Test Level Symbol Min Typ Max Unit |
Número de pieza similar - TS83102G0B |
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Descripción similar - TS83102G0B |
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