RMLV0408E Series

R10DS0206EJ0200 Rev.2.00

Page 5 of 10

2016.1.12

AC Characteristics

Test Conditions (Vcc = 2.7V ~ 3.6V, Ta = -40 ~ +85°C)

 Input rise and fall time: 5ns

 Input and output timing reference level: 1.4V

 Output load: See figures (Including scope and jig)

Read Cycle

Parameter

Symbol

Min.

Max.

Unit

Note

Read cycle time

45

─

ns

Address access time

─

45

ns

Chip select access time

─

45

ns

Output enable to output valid

─

22

ns

Output hold from address change

10

─

ns

Chip select to output in low-Z

10

─

ns

7,8

Output enable to output in low-Z

5

─

ns

7,8

Chip deselect to output in high-Z

0

18

ns

7,8,9

Output disable to output in high-Z

0

18

ns

7,8,9

Write Cycle

Parameter

Symbol

Min.

Max.

Unit

Note

Write cycle time

45

─

ns

Address valid to write end

35

─

ns

Chip select to write end

35

─

ns

Write pulse width

35

─

ns

10

Address setup time to write start

0

─

ns

Write recovery time from write end

0

─

ns

Data to write time overlap

25

─

ns

Data hold from write end

0

─

ns

Output enable from write end

5

─

ns

7

Output disable to output in high-Z

0

18

ns

7,9

Write to output in high-Z

0

18

ns

7,9

Note

7. This parameter is sampled and not 100% tested.

min, for any device.

9.

referred to the I/O levels.

A write starts when both of CS# and WE# become active

A write is performed during the overlap of a low CS#, a low WE#

A write ends when any of CS#, WE# becomes inactive.

I/O

1.4V