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UPD48576209F1 Datasheet(PDF) 39 Page - Renesas Technology Corp

No. de pieza UPD48576209F1
Descripción Electrónicos  576M-BIT Low Latency DRAM
Download  54 Pages
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Fabricante Electrónico  RENESAS [Renesas Technology Corp]
Página de inicio  http://www.renesas.com
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UPD48576209F1 Datasheet(HTML) 39 Page - Renesas Technology Corp

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µµµµPD48576209F1, µµµµPD48576218F1, µµµµPD48576236F1
R10DS0256EJ0101 Rev. 1.01
Page 39 of 53
Jan. 15, 2016
2.18 Input Slew Rate Derating
Table 2-8
on page 40 and Table 2-9 on page 41 define the address, command, and data setup and hold derating values.
These values are added to the default tAS/tCS/tDS and tAH/tCH/tDH specifications when the slew rate of any of these
input signals is less than the 2 V/ns the nominal setup and hold specifications are based upon.
To determine the setup and hold time needed for a given slew rate, add the tAS/tCS default specification to the “tAS/tCS
VREF to CK/CK# Crossing” and the tAH/tCH default specification to the “tAH/tCH CK/CK# Crossing to VREF” derated
values on Table 2-8. The derated data setup and hold values can be determined in a like manner using the “tDS VREF to
CK/CK# Crossing” and “tDH to CK/CK# Crossing to VREF” values on Table 2-9.
The derating values on Table 2-8 and Table 2-9 apply to all speed grades.
The setup times on Table 2-8 and Table 2-9 represent a rising signal. In this case, the time from which the rising signal
crosses VIH(AC) MIN to the CK/CK# cross point is static and must be maintained across all slew rates. The derated setup
timing represents the point at which the rising signal crosses VREF(DC) to the CK/CK# cross point. This derated valueis
calculated by determining the time needed to maintain the given slew rate and the delta between VIH(AC) MIN and the
CK/CK# cross point. The setup values in Table 2-8 and Table 2-9 are also valid for falling signals (with respect to VIL[AC]
MAX and the CK/CK# cross point).
The hold times in Table 2-8 and Table 2-9 represent falling signals. In this case, the time from the CK/CK# cross point
to when the signal crosses VIH(DC) MIN is static and must be maintained across all slew rates. The derated hold timing
represents the delta between the CK/CK# cross point to when the falling signal crosses VREF(DC). This derated value is
calculated by determining the time needed to maintain the given slew rate and the delta between the CK/CK# cross point
and VIH(DC). The hold values in Table 2-8 and Table 2-9 are also valid for rising signals (with respect to VIL[DC] MAX and
the CK and CK# cross point).
Note The above descriptions also pertain to data setup and hold derating when CK/CK# are replaced with DK/DK#.


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