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M058LDE Datasheet(PDF) 8 Page - List of Unclassifed Manufacturers |
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M058LDE Datasheet(HTML) 8 Page - List of Unclassifed Manufacturers |
8 / 86 page M051 DN/DE Oct. 05, 2015 Page 8 of 86 Rev 1.03 2 FEATURES Core ARM® Cortex ® -M0 core running up to 50 MHz One 24-bit system timer Supports Low Power Sleep mode A single-cycle 32-bit hardware multiplier NVIC for the 32 interrupt inputs, each with 4-levels of priority Supports Serial Wire Debug (SWD) interface and two watchpoints/four breakpoints Provides hardware divider and supports signed 32-bit dividend, 16-bit divisor operation Wide Operating Voltage Range: 2.5V to 5.5V Memory 8KB/16KB/32KB/64KB Flash for program memory (APROM) 4KB Flash for data memory (Data Flash) 4KB Flash for loader (LDROM) 4KB SRAM for internal scratch-pad RAM (SRAM) Clock Control Programmable system clock source 22.1184 MHz internal oscillator 4~24 MHz external crystal input 10 kHz low-power oscillator for Watchdog Timer and wake-up in Sleep mode PLL allows CPU operation up to the maximum 50 MHz I/O Port Up to 40 general-purpose I/O (GPIO) pins for LQFP-48 package Four I/O modes: Quasi-bidirectional Push-Pull output Open-Drain output Input only with high impendence TTL/Schmitt trigger input selectable I/O pin can be configured as interrupt source with edge/level setting Supports high driver and high sink I/O mode Configurable I/O mode after POR Timer Provides four channel 32-bit timers; one 8-bit pre-scale counter with 24-bit up-timer for each timer Independent clock source for each timer 24-bit timer value is readable through TDR (Timer Data Register) Provides One-shot, Periodic and Toggle operation modes Provides event counter function Provides external capture/reset counter function Two more timer clock sources from external trigger and internal 10 kHz TIMER wake-up function External capture input source selected from ACMP or TxEX Toggle mode output pins selected from TxEX or TMx Inter-Timer trigger mode WDT (Watchdog Timer) |
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