Motor de Búsqueda de Datasheet de Componentes Electrónicos |
|
TPS2372-4RGWT Datasheet(PDF) 3 Page - Texas Instruments |
|
|
TPS2372-4RGWT Datasheet(HTML) 3 Page - Texas Instruments |
3 / 43 page 1 2 3 4 DEN CLSA NC 15 14 13 12 VSS RTN PG VSS NC 5 VDD 11 RTN 3 TPS2372 www.ti.com SLUSCM4 – OCTOBER 2017 Product Folder Links: TPS2372 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated 5 Pin Configuration and Functions RGW Package 20-Pin VQFN Top View Pin Functions PIN I/O DESCRIPTION NAME NO. VDD 1 I Connect to positive PoE input power rail. Bypass with 0.1 µF to VSS. DEN 2 I/O Connect a 24.9 kΩ resistor from DEN to VDD to provide the PoE detection signature. Pull DEN to VSS to disable the pass MOSFET during powered operation. CLSA 3 O Connect a resistor from CLSA to VSS to program the first classification current. VSS 4, 5 — Connect to negative power rail derived from PoE source. CLSB 6 O Connect a resistor from CLSB to VSS to program the second classification current. REF 7 O Internal 1.5 V voltage reference. Connect a 49.9kΩ_1% resistor from REF to VSS. AMPS_CTL 8 O Automatic MPS control. Connect a resistor with appropriate power rating (to support the MPS current) from AMPS_CTL to VSS to program the MPS current amplitude. Leave AMPS_CTL open to disable the automatic MPS function. MPS_DUTY 9 I MPS duty cycle select input, referenced to VSS, internally driven by a precision current source with voltage limited to less than ~5.5V. A resistor connected to VSS determines if the MPS duty cycle selected is either 5.4% (open), 8.1% (~60.4 kΩ) or 12.5% (short). AUTCLS 10 I Autoclass enable input. Internally pulled-up to 5.5 V internal rail during classification only, pulled down in other circumstances to minimize consumption. Pull low (to VSS) to enable the Autoclass function during classification. Leave open otherwise. RTN 11, 12 — Drain of PoE pass MOSFET. Return line from the load to the controller. PG 13 O Power Good output. Open-drain, active-high output referenced to RTN. NC 14, 15 — No connect IRSHDL_E N 16 I PSE inrush delay (~81.5 ms) enable, referenced to RTN, internally pulled-up to 5.5 V internal rail. Leave open to enable the inrush delay. TPL 17 O PSE allocated power outputs, binary coded. Open-drain, active-low outputs referenced to RTN. TPH 18 O BT 19 O Indicates that a PSE applying an IEEE802.3bt (Type 3 or 4) mutual identification scheme has been identified. Open-drain, active-low output referenced to RTN. NC 20 — No connect pin. Leave open. Pad — — The exposed thermal pad must be connected to VSS. A large fill area is required to assist in heat dissipation. |
Número de pieza similar - TPS2372-4RGWT |
|
Descripción similar - TPS2372-4RGWT |
|
|
Enlace URL |
Política de Privacidad |
ALLDATASHEET.ES |
¿ALLDATASHEET es útil para Ud.? [ DONATE ] |
Todo acerca de Alldatasheet | Publicidad | Contáctenos | Política de Privacidad | Intercambio de Enlaces | Lista de Fabricantes All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |