Motor de Búsqueda de Datasheet de Componentes Electrónicos |
|
TPS63710DRRT Datasheet(PDF) 9 Page - Texas Instruments |
|
|
TPS63710DRRT Datasheet(HTML) 9 Page - Texas Instruments |
9 / 36 page GND + - VBG FB VOUT VREF CAP gain = 1 0.9 noise filter gain stage internal 100k SW L C OUT Copyright © 2017, Texas Instruments Incorporated C CAP R 1 R 2 CAP C k C R fc ´ W ´ = ´ ´ = 100 2 1 2 1 p p 9 TPS63710 www.ti.com SLVSD44 – SEPTEMBER 2017 Product Folder Links: TPS63710 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated 7.3 Feature Description 7.3.1 Low Noise Reference System The reference system in the TPS63710 uses an external filter capacitor on the CAP pin. This reduces the low- frequency (1/f) noise in a range from a lower limit up to around 100kHz. The lower limit is defined by the corner frequency of the RC filter from the internal 100-kΩ resistor and an external capacitor on the CAP pin. The corner frequency is defined by Equation 1. (1) In order to minimize the noise on the output voltage, the TPS63710 uses an architecture where the output voltage setting is done by changing the reference voltage which then is filtered. The gain stage therefore does not have to have a large gain in order to not increase the noise level. VBG is the internal bandgap reference voltage, optimized for low noise. Its output voltage is amplified and inverted and then filtered. The voltage on the CAP pin is the reference for the gain stage. The connection from CAP to the external capacitor should be as short as possible and be kept away from noisy traces. The gain stage has a small gain of 1/0.9. The voltage at VREF is negative and lower than the output voltage by the gain factor of the gain stage. Please also see Setting the Output Voltage. Figure 9 shows the low noise architecture. Figure 9. Low Noise Architecture 7.3.2 Duty Cycle The duty cycle referred to in this data sheet is the duty cycle at the SW pin. By definition, from the PWM operation, the CP pin has the inverse duty cycle of 1-D. As a first approximation, the duty cycle is defined as |VOUT| / VIN. However, the actual duty cycle is larger, due to losses, and must remain below 70% for a robust design. 7.3.3 Enable The device is enabled when the EN pin is set to high. With EN set to low, the device shuts down. After EN is set high, the capacitor CCP (from CP to SW) is pre-charged with about 50mA. After the start-up delay time tdelay, the device starts switching and ramps the output voltage to its target value. See Soft-Start. The EN pin must be set externally to high or low. An internal pull-down resistor of about 400 kΩ is connected and keeps EN low, if a low is detected internally and afterwards the pin is floating. When a high level is detected, the internal resistor is disconnected. 7.3.4 Undervoltage Lockout An undervoltage lockout circuit prevents the device from starting up and operating, if the supply voltage is too low. The device automatically shuts down the converter when the VAUX voltage falls below the VUVLO threshold. There is hysteresis to prevent oscillation with high impedance supply voltage sources. Once the threshold plus hysteresis is exceeded, the device enters soft-start. Undervoltage lockout is sensed on the VAUX voltage, as this is the internal supply for the control loop and logic. |
Número de pieza similar - TPS63710DRRT |
|
Descripción similar - TPS63710DRRT |
|
|
Enlace URL |
Política de Privacidad |
ALLDATASHEET.ES |
¿ALLDATASHEET es útil para Ud.? [ DONATE ] |
Todo acerca de Alldatasheet | Publicidad | Contáctenos | Política de Privacidad | Intercambio de Enlaces | Lista de Fabricantes All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |