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AD7903BRQZ-RL7 Datasheet(PDF) 19 Page - Analog Devices |
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AD7903BRQZ-RL7 Datasheet(HTML) 19 Page - Analog Devices |
19 / 29 page AD7903 Data Sheet Rev. B | Page 18 of 28 CS MODE CS Mode, 3-Wire Interface Without Busy Indicator CS mode, using a 3-wire interface without a busy indicator, is usually used when a single AD7903 is connected to a SPI- compatible digital host. The connection diagram is shown in Figure 39, and the corresponding timing diagram is shown in Figure 40. With SDIx tied to VIOx, a rising edge on CNVx initiates a conversion, selects CS mode, and forces SDOx to high impedance. When a conversion is initiated, it continues until completion, irrespective of the state of CNVx. This can be useful, for instance, to bring CNVx low to select other SPI devices, such as analog multiplexers. However, to avoid generation of the busy signal indicator, CNVx must be returned high before the minimum conversion time elapses and then held high for the maximum possible conversion time. When the conversion is complete, the AD7903 enters the acquisition phase and powers down. When CNVx goes low, the MSB is automatically output onto SDOx. The remaining data bits are clocked by subsequent SCKx falling edges. The data is valid on both SCKx edges. Although the rising edge can be used to capture the data, a digital host using the falling edge of SCKx allows a faster reading rate, provided that it has an acceptable hold time. After the 16th SCKx falling edge or when CNVx goes high (whichever occurs first), SDOx returns to high impedance. Figure 39. CS Mode, 3-Wire Interface Without Busy Indicator Connection Diagram (SDIx High) Figure 40. CS Mode, 3-Wire Interface Without Busy Indicator Serial Interface Timing (SDI High) AD7903 SDIx SDOx CNVx SCKx CONVERT DATA IN CLK DIGITAL HOST VIOx SDIx = 1 tCNVH tCONV tCYC CNVx ACQUISITION ACQUISITION tACQ tSCK tSCKL CONVERSION SCKx tEN tHSDO 12 3 14 15 16 tDSDO tDIS tSCKH SDOx D15 D14 D13 D1 D0 |
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