AD9681-125EBZ datasheet(8/41 Pages) AD

No. de pieza	AD9681-125EBZ

Descripción Electrónicos	1.8 V Analog-to-Digital Converter

Download	41 Pages

Scroll/Zoom	100%

Fabricante Electrónico	AD [Analog Devices]

Página de inicio	http://www.analog.com

Logo

8 / 41 page

Data Sheet

AD9681

Rev. C | Page 7 of 40

SWITCHING SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, unless otherwise noted.

Table 4.

Parameter

1, 2

Symbol

Temp

Min

Typ

Max

Unit

CLOCK3

Input Clock Rate

Full

10

1000

MHz

Conversion Rate4

Full

10

125

MSPS

Clock Pulse Width High

tEH

Full

4.00

ns

Clock Pulse Width Low

tEL

Full

4.00

ns

OUTPUT PARAMETERS3

Propagation Delay

tPD

Full

1.5

2.3

3.1

ns

Rise Time (20% to 80%)

tR

Full

300

ps

Fall Time (20% to 80%)

tF

Full

300

ps

FCO±1, FCO±2 Propagation Delay

tFCO

Full

1.5

2.3

3.1

ns

DCO±1, DCO±2 Propagation Delay5

tCPD

Full

tFCO + (tSAMPLE/16)

ns

DCO±1, DCO±2 to Data Delay5

tDATA

Full

(tSAMPLE/16) − 300

(tSAMPLE/16)

(tSAMPLE/16) + 300

ps

DCO±1, DCO±2 to FCO±1, FCO±2 Delay5

tFRAME

Full

(tSAMPLE/16) − 300

(tSAMPLE/16)

(tSAMPLE/16) + 300

ps

Lane Delay

tLD

90

ps

Data to Data Skew

tDATA-MAX − tDATA-MIN

Full

±50

±200

ps

Wake-Up Time (Standby)

25°C

250

ns

Wake-Up Time (Power-Down)6

25°C

375

μs

Pipeline Latency

Full

16

Clock

cycles

APERTURE

Aperture Delay

tA

25°C

1

ns

Aperture Uncertainty (Jitter)

tJ

25°C

135

fs rms

Out-of-Range Recovery Time

25°C

1

Clock

cycles

1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.

2 Measured on standard FR-4 material.

3 Adjustable using the SPI. The conversion rate is the clock rate after the divider.

4 The maximum conversion rate is based on two-lane output mode. See the Digital Outputs and Timing section for the maximum conversion rate in one-lane output mode.

5 tSAMPLE/16 is based on the number of bits in two LVDS data lanes. tSAMPLE = 1/fSAMPLE.

6 Wake-up time is defined as the time required to return to normal operation from power-down mode.

Número de pieza similar - AD9681-125EBZ

Fabricante Electrónico	No. de pieza	Datasheet	Descripción Electrónicos
Analog Devices	AD9681-125EBZ	1Mb / 40P	Octal, 14-Bit, 125 MSPS, Serial LVDS, 1.8 V Analog-to-Digital Converter REV. A

More results

Descripción similar - AD9681-125EBZ

Fabricante Electrónico	No. de pieza	Datasheet	Descripción Electrónicos
Analog Devices	AD9266	1Mb / 33P	1.8 V Analog-to-Digital Converter
	AD9634	1Mb / 31P	1.8 V Analog-to-Digital Converter
	AD9601	972Kb / 33P	1.8 V Analog-to-Digital Converter
	AD9211	1Mb / 29P	1.8 V Analog-to-Digital Converter
	AD9626	1Mb / 37P	1.8 V Analog-to-Digital Converter
	AD9635	995Kb / 37P	1.8 V Analog-to-Digital Converter
	AD9637	1,012Kb / 41P	1.8 V Analog-to-Digital Converter
	AD9230	1Mb / 33P	1.8 V Analog-to-Digital Converter
	AD9257	1Mb / 41P	1.8 V Analog-to-Digital Converter
	AD9246	1,007Kb / 45P	1.8 V Analog-to-Digital Converter
	AD9434	921Kb / 29P	1.8 V Analog-to-Digital Converter

More results

AD9681-125EBZ Datasheet(PDF) 8 Page - Analog Devices

AD9681-125EBZ Datasheet(HTML) 8 Page - Analog Devices

Número de pieza similar - AD9681-125EBZ

Descripción similar - AD9681-125EBZ

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41

Datasheet Descarga

Enlace URL