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AD9644-155KITZ Datasheet(PDF) 9 Page - Analog Devices |
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AD9644-155KITZ Datasheet(HTML) 9 Page - Analog Devices |
9 / 45 page AD9644 Data Sheet Rev. C | Page 8 of 44 SWITCHING SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, 1.75 V p-p differential input, VIN = −1.0 dBFS differential input, and DCS enabled, unless otherwise noted. Table 4. AD9644-80 AD9644-155 Parameter Temperature Min Typ Max Min Typ Max Unit CLOCK INPUT PARAMETERS Input Clock Rate Full 640 640 MHz Conversion Rate1 Full 40 80 40 155 MSPS CLK Period—Divide-by-1 Mode (tCLK) Full 12.5 6.45 ns CLK Pulse Width High (tCH) Divide-by-1 Mode, DCS Enabled Full 3.75 6.25 8.75 1.935 3.225 4.515 ns Divide-by-1 Mode, DCS Disabled Full 5.95 6.25 6.55 3.065 3.225 3.385 ns Divide-by-2 Mode Through Divide-by-8 Mode Full 0.8 0.8 ns Aperture Delay (tA) Full 0.78 0.78 ns Aperture Uncertainty (Jitter, tJ) Full 0.125 0.125 ps rms DATA OUTPUT PARAMETERS Data Output Period or UI (Unit Interval) Full 1/(20 × fCLK) 1/(20 × fCLK) Seconds Data Output Duty Cycle 25°C 50 50 % Data Valid Time 25°C 0.78 0.74 UI PLL Lock Time (tLOCK) 25°C 4 4 µs Wake Up Time (Standby) 25°C 5 5 µs Wake Up Time (Power-Down)2 25°C 2.5 2.5 ms Pipeline Delay (Latency) Full 23 24 23 24 CLK cycles Data Rate per Channel (NRZ) 25°C 1.6 3.1 Gbps Deterministic Jitter 25°C 40 40 ps Random Jitter at 1.6 Gbps 25°C 9.5 ps rms Random Jitter at 3.2 Gbps 25°C 5.2 5.2 ps rms Output Rise/Fall Time 25°C 50 50 ps TERMINATION CHARACTERISTICS Differential Termination Resistance 25°C 100 100 Ω OUT-OF-RANGE RECOVERY TIME 25°C 2 2 CLK cycles 1 Conversion rate is the clock rate after the divider. 2 Wake-up time is defined as the time required to return to normal operation from power-down mode. |
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