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AD9262 Datasheet(PDF) 8 Page - Analog Devices |
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AD9262 Datasheet(HTML) 8 Page - Analog Devices |
8 / 33 page AD9262 Rev. A | Page 7 of 32 SWITCHING SPECIFICATIONS All power supplies set to 1.8 V, 640 MHz sample rate, 0.5 V internal reference, PLL disabled, 40 MSPS output data rate, AIN = −2.0 dBFS unless otherwise noted. Table 5. Parameter1 Temp Min Typ Max Unit CLOCK INPUT (USING CLOCK MULTIPLIER) Conversion Rate Full 30 160 MSPS CLK± Period Full 6.25 33 ns CLK± Duty Cycle Full 40 50 60 % CLOCK INPUT (DIRECT CLOCKING) Conversion Rate Full 608 640 672 MSPS CLK± Period Full 1.49 1.5625 1.64 ns CLK± Duty Cycle Full 40 50 60 % DATA OUTPUT PARAMETERS Output Data Rate Full 20 160 MSPS DCO to Data Skew (tSKEW)2 Full 3 ns Sample Latency3 Full 960 Cycles4 WAKE-UP TIME5 Power-Down Power Full 3 μs Standby Power Full 9 μs Sleep Power Full 15 μs OUT-OF-RANGE RECOVERY TIME3 Full 960 Cycles4 SERIAL PORT INTERFACE6 SCLK Period Full 40 ns SCLK Pulse Width High Time (tSHIGH) Full 16 ns SCLK Pulse Width Low Time (tSLOW) Full 16 ns SDIO to SCLK Setup Time (tSDS) Full 5 ns SDIO to SCLK Hold Time (tSDH) Full 2 ns CSB to SCLK Setup Time (tSS) Full 5 ns CSB to SCLK Hold Time (tSH) Full 2 ns 1 See the AN-83 5 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions. 2 Data skew is measured from DCO 50% transition to data (D0x to D15x) 50% transition, with 5 pF load. 3 Typical measured value for the AD9262BCPZ-10. For the AD9262BCPZ-5 and the AD9262BCPZ, typical values double and quadruple the number of cycles, respectively. 4 Cycles refers to modulator clock cycles. 5 Wake-up time is dependent on the value of the decoupling capacitor, value shown with 10uF capacitor on VREF and CFILT. 6 See Figure 60 and the Serial Port Interface (SPI) section. Timing Diagram DCO D0x TO D15x tSKEW Figure 2. Timing Diagram |
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