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FIN3383MTD Datasheet(Hoja de datos) 7 Page - Fairchild Semiconductor

No. de Pieza. FIN3383MTD
Descripción  Low Voltage 28-Bit Flat Panel Display Link Serializers
Descarga  9 Pages
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Fabricante  FAIRCHILD [Fairchild Semiconductor]
Página de inicio  http://www.fairchildsemi.com
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FIGURE 9. Transmitter Output Pulse Bit Position
Note: This jitter pattern is used to test the jitter response (Clock Out) of the device over the power supply range with worst jitter
±3ns (cycle-to-cycle) clock
input. The specific test methodology is as follows:
Switching input data TxIn0 to TxIn20 at 0.5 MHz, and the input clock is shifted to left
−3ns and to the right +3ns when data is HIGH.
The
±3 ns cycle-to-cycle input jitter is the static phase error between the two clock sources. Jumping between two clock sources to simulate the worst
case of clock edge jump (3 ns) from graphical controllers. Cycle-to-cycle jitter at TxCLK out pin should be measured cross VCC range with 100mV noise
(VCC noise frequency <2 MHz).
FIGURE 10. Timing Diagram of Transmitter Clock Input with Jitter




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