SN65MLVD128

SN65MLVD129

SLLS586 − MARCH 2004

www.ti.com

5

SWITCHING CHARACTERISTICS

over recommended operating conditions unless otherwise noted

PARAMETER

TEST CONDITIONS

MIN

TYP(1)

MAX

UNIT

tpLH

Propagation delay time, low-to-high-level output

See Figure 5

1

3

ns

tpHL

Propagation delay time, high-to-low-level output

1

3

ns

tr

Differential output signal rise time

1

2

ns

tf

Differential output signal fall time

1

2

ns

tsk(p)

Pulse skew (|tpHL − tpLH|)

100

ps

tsk(o)

Output skew

160

ps

tsk(bb)

Bank-to-bank skew(2)

100

ps

tsk(pp)

Part-to-part skew(3)

800

ps

tjit(per)

Period jitter, rms (1 standard deviation)(4)

100 MHz clock input, All channels

enabled

1

3

ps

tjit(c−c)

Cycle-to-cycle jitter(4)

100 MHz clock input, All channels

enabled

20

ps

tjit(pp)

Peak-to-peak jitter(4)

200 Mbps 215−1 PRBS input, All

channels enabled

46

110

ps

tpZH

Enable time, high-impedance-to-high-level output

See Figure 6

7

ns

tpZL

Enable time, high-impedance-to-low-level output

See Figure 6

7

ns

tpHZ

Disable time, high-level-to-high-impedance output

See Figure 6

7

ns

tpLZ

Disable time, low-level-to-high-impedance output

See Figure 6

7

ns

(1) All typical values are at 25°C and with a 3.3-V supply voltage.

(2) tsk(bb), which only applies to the SN65MLVD129, is the magnitude of the difference between the tPLH and tPHL of two outputs of any bank.

(3) tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate

with the same supply voltages, at the same temperature, and have identical packages and test circuits.

(4) Stimulus jitter has been subtracted from the numbers.