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MT9V032 Datasheet(PDF) 23 Page - ON Semiconductor |
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MT9V032 Datasheet(HTML) 23 Page - ON Semiconductor |
23 / 61 page MT9V032 www.onsemi.com 23 Table 8. REGISTER DESCRIPTIONS 0X09 (9) SHUTTER WIDTH 2 5 Column Flip Read out columns from right to left (mirrored). When set, column readout starts from column (Col Start + Window Width) and continues down to (Col Start + 1). When clear, readout starts at Col Start and continues to (Col Start + Window Width − 1). This ensures that the starting color is maintained. 0 Y 0, 1 W 6 Show Dark Rows When set, the programmed dark rows is output before the active window. Frame valid is thus asserted earlier than normal. This has no effect on integration time or frame rate. Whether the dark rows are shown in the image or not the definition frame start is before the dark rows are read out. 0 Y 0, 1 W 7 Show Dark Columns When set, the programmed dark columns are output before the active pixels in a line. Line valid is thus asserted earlier than normal, and the horizontal blank time gets shorter by 18 pixel clocks. 0 Y 0, 1 W 9:8 Reserved Reserved. 3 0X0E (14) MONITOR MODE 0 Monitor Mode Enable Setting this bit puts the sensor into a cycle of sleeping for five minutes, and waking up to capture a programmable number of frames (R0xC0). Clearing this bit resumes nor- mal operation. 0 Y 0, 1 W 0X0F (15) PIXEL OPERATION MODE 2 Color/Mono Should be set according to sensor type: 0 = Monochrome. 1 = Color. 0 Y 0, 1 W 6 High Dynamic Range 0 = Linear operation. 1 = High Dynamic Range. Voltage and shutter width must be correctly set for saturation control to operate. 0 Y 0, 1 W 0X1B (27) LED_OUT CONTROL 0 Disable LED_OUT Disable LED_OUT output. When cleared, the output pin LED_OUT is pulsed high when the sensor is undergoing exposure. 0 Y 0, 1 W 1 Invert LED_OUT Invert polarity of LED_OUT output. When set, the output pin LED_OUT is pulsed low when the sensor is undergoing exposure. 0 Y 0, 1 W 0X1C (28) ADC RESOLUTION CONTROL 1:0 ADC Mode 0 = Invalid. 1 = Invalid. 2 = 10−bit linear. 3 = 12−to10−bit companding. 2 Y 2, 3 W 0X2C (44) VREF_ADC CONTROL 2:0 VREF_ADC Voltage Level 0 = VREF_ADC = 1.0V. 1 = VREF_ADC = 1.1V. 2 = VREF_ADC = 1.2V. 3 = VREF_ADC = 1.3V. 4 = VREF_ADC = 1.4V. 5 = VREF_ADC = 1.5V. 6 = VREF_ADC = 1.6V. 7 = VREF_ADC = 2.1V. Range: 1.0–2.1V; Default: 1.4V VREF_ADC for ADC. 4 N 0–7 W 0X31 (49) V1 CONTROL 4:0 V1 voltage level V_Step = bits (4:0) x 62.5mV + 0.5625V. Range: 0.5625 − 2.5V; Default: 2.375V. Usage: V_Step1 HiDy voltage. 1D (29) N 0–31 W 0X32 (50) V2 CONTROL |
Número de pieza similar - MT9V032_17 |
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Descripción similar - MT9V032_17 |
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