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ADS5522 Datasheet(PDF) 6 Page - Burr-Brown (TI) |
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ADS5522 Datasheet(HTML) 6 Page - Burr-Brown (TI) |
6 / 30 page ADS5542 SBAS308A − MAY 2004 − REVISED MARCH 2005 www.ti.com 6 TIMING CHARACTERISTICS NOTE: It is recommended that the loading at CLKOUT and all data lines are accurately matched to ensure that the above timing matches closely with the specified values. 16.5 Clock Cycles Input Clock Output Clock Data Out (D0−D13) Analog Input Signal Sample N N+ 1 N+2 N+ 3 N+4 N+ 1 4 N+ 1 6 N+ 1 7 t A t HOLD Data Invalid N+ 1 5 t START t SETUP tPDI = tSTART + t SETUP N − 17 N − 16 N − 15 N − 14 N − 13 N − 3 N − 2 N − 1 N tEND Figure 1. Timing Diagram TIMING CHARACTERISTICS(1)(2) Typical values at TA = +25 °C, full temperature range is TMIN = −40°C to tMAX = +85°C, sampling rate = 80MSPS, 50% clock duty cycle, AVDD = DRVDD = 3.3V, and 3VPP differential clock, unless otherwise noted.(2) PARAMETER DESCRIPTION MIN TYP MAX UNIT Switching Specification Aperture delay, tA Input CLK falling edge to data sampling point 1 ns Aperture jitter (uncertainty) Uncertainty in sampling instant 300 fs Data setup time, tSETUP Data valid(3) to 50% of CLKOUT rising edge 3.2 4.2 ns Data hold time, tHOLD 50% of CLKOUT rising edge to data becoming invalid(3) 1.8 3 ns Input clock to output data valid start, tSTART(4) Input clock to Data valid start delay 3.8 5 ns Input clock to output data valid end, tEND(4) Input clock to Data valid end delay 8.4 11 ns Data rise time, tRISE Data rise time measured from 20% to 80% of DRVDD 5.6 6.1 ns Data fall time, tFALL Data fall time measured from 80% to 20% of DRVDD 4.4 5.1 ns Output enable (OE) to data output delay Time required for outputs to have stable timings with regard to Input Clock(5) after OE is activated 1000 Clock Cycles (1) Timing parameters are ensured by design and characterization, and not tested in production. (2) See Table 5 in the Application Information section for timing information at additional sampling frequencies. (3) Data valid refers to 2.0V for LOGIC HIGH and 0.8V for LOGIC LOW. (4) Refer to the Output Information section for details on using the input clock for data capture. (5) Data outputs are available within a clock from assertion of OE; however it takes 1000 clock cycles to ensure stable timing with respect to input clock. |
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