CAT34TS00

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6

Figure 4. Acknowledge Timing

ACKNOWLEDGE

1

START

SCL FROM

MASTER

89

DATA OUTPUT

FROM TRANSMITTER

DATA OUTPUT

FROM RECEIVER

30%

30%

70%

30%

70%

30%

30%

70%

70%

70%

70%

70%

70%

SCL

SDA IN

Figure 5. Bus Timing

SDA OUT

30%

70%

Write Operations

To write data to one of the internal registers, the Master

creates a START condition on the bus, and then sends out the

appropriate Slave address (with the R/W bit set to ‘0’),

followed by the register address, followed by two data bytes.

The matching Slave will acknowledge the Slave address,

register address and each data byte (Figure 6). The Master

then ends the session by creating a STOP condition on the

bus. The STOP completes the register update.

Read Operations

Immediate Read

A CAT34TS00 presented with a Slave address containing

a ‘1’ in the R/W position will acknowledge the Slave address

and will then start transmitting the content of the register at

the current address pointer location. The Master stops this

transmission by responding with NoACK, followed by a

STOP (Figure 7).

Selective Read

The Read operation can be started from a specific address,

by preceding the Immediate Read sequence with a ‘data less’

Write sequence. The Master sends out a START, Slave

address and register address, but rather than following up

with data (as in a Write operation), the Master then issues

another START and continues with an Immediate Read

sequence (Figure 8).

Figure 6. Temperature Sensor Register Write

SLAVE

REGISTER

ADDRESS

ADDRESS

TS

S

A

C

K

BUS ACTIVITY:

MASTER

SDA LINE

SLAVE

S

T

A

R

T

A

C

K

DATA (MSB)

DATA (LSB)

A

C

K

A

C

K

A

C

K

A

C

K

P

S

T

O

P