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CAT34TS00 Datasheet(PDF) 3 Page - ON Semiconductor

No. de pieza CAT34TS00
Descripción Electrónicos  1.8 V Digital Temperature Sensor
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Fabricante Electrónico  ONSEMI [ON Semiconductor]
Página de inicio  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

CAT34TS00 Datasheet(HTML) 3 Page - ON Semiconductor

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CAT34TS00
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Table 4. A.C. CHARACTERISTICS (VCC = 1.7 V to 1.9 V, TA = −20°C to +125°C)
Symbol
Parameter
100 kHz
400 kHz
Units
Min
Max
Min
Max
FSCL (Note 5)
Clock Frequency
10
100
10
400
kHz
tHIGH
High Period of SCL Clock
4
0.6
ms
tLOW
Low Period of SCL Clock
4.7
1.3
ms
tTIMEOUT (Note 6)
SMBus SCL Clock Low Timeout
25
35
25
35
ms
tR (Note 7)
SDA and SCL Rise Time
1000
300
ns
tF (Note 7)
SDA and SCL Fall Time
300
300
ns
tSU:DAT
Input Data Setup Time
250
100
ns
tSU:STA
START Condition Setup Time
4.7
0.6
ms
tHD:STA
START Condition Hold Time
4
0.6
ms
tSU:STO
STOP Condition Setup Time
4
0.6
ms
tBUF
Bus Free Time Between STOP and START
4.7
1.3
ms
tHD:DAT
Input Data Hold Time
0
0
ns
tDH (Note 7)
Output Data Hold Time
120
3450
120
900
ns
Ti (Note 7)
Noise Pulse Filtered at SCL and SDA Inputs
50
50
ns
tPU (Note 8)
Power-Up Delay to Valid Temperature Recording
100
100
ms
5. Timing reference points are set at 30%, respectively 70% of VCC, as illustrated in Figure 5. Bus loading must be such as to allow meeting
the VIL and VOL as well as all other timing requirements. The minimum clock frequency of 10 kHz is an SMBus recommendation; the minimum
operating clock frequency is limited only by the SMBus time−out. The device also meets the Fast and Standard I2C specifications, except
that Ti and tDH are shorter.
6. For the CAT34TS00, the interface will reset itself and will release the SDA line if the SCL line stays low beyond the tTIMEOUT limit. The time−out
count takes place when SCL is low in the time interval between START and STOP.
7. In a “Wired−OR” system (such as I2C or SMBus), SDA rise time is determined by bus loading. Since each bus pull−down device must be
able to sink the (external) bus pull−up current (in order to meet the VIL and/or VOL limits), it follows that SDA fall time is inherently faster than
SDA rise time. SDA rise time can exceed the standard recommended tR limit, as long as it does not exceed tLOW − tDH − tSU:DAT, where tLOW
and tDH are actual values (rather than spec limits). A shorter tDH leaves more room for a longer SDA tR, allowing for a more capacitive bus
or a larger bus pull−up resistor.
8. The first valid temperature recording can be expected after tPU at nominal supply voltage.
Table 5. PIN CAPACITANCE (TA = 25°C, VCC = 1.9 V, f = 400 kHz)
Symbol
Parameter
Test Conditions/Comments
Min
Max
Unit
CIN
SDA, EVENT Pin Capacitance
VIN = 0
8
pF
Input Capacitance (other pins)
VIN = 0
6
pF
Table 6. INPUT IMPEDANCE
Symbol
Parameter
Test Conditions
Min
Max
Unit
ZEIL
Input Impedance for A0, A1, A2 Pins
VIN < 0.3 * VCC
30
k
W
ZEIH
Input Impedance for A0, A1, A2 Pins
VIN > 0.7 * VCC
800
k
W


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